Nonvolatile memory devices are used to store data such that removal of the power to the device does not result in the data being lost. Instead, the data continues to be stored despite the removal of power. FIG. 1 depicts one such conventional memory device 10. The conventional memory device 10 includes an array 12 having a number of cells (not explicitly shown in FIG. 1). The conventional memory device 10 also includes a conventional row decoder 14, a conventional column decoder 16, conventional sense amplification circuitry 18, conventional high voltage switches 20, a conventional data multiplexer 22, conventional programming logic 24, and a conventional input/ouput (I/O) bus 26.
The conventional row decoder 14 and conventional column decoder 16 are used to address memory cells within the array 12. The conventional column decoder 16, for example, routes data in the addressed columns of the conventional array 12 to the conventional sense amplification circuitry 18. The conventional sense amplification circuitry 18 typically includes a number of sense amplifiers (not explicitly shown) which read the data in the addressed columns. The conventional data multiplexer 22 drives the conventional I/O bus 26 to output the data. The conventional programming logic 24 receives from the conventional I/O bus 26 the data to be programmed and controls the high voltage switches 8. Thus, using the conventional memory device 10, data stored in the nonvolatile memory 10 can be read and stored.
Although the conventional memory 10 functions, one of ordinary skill in the art will readily recognize that the conventional, single bank memory 10 may be incapable of performing read-while-write operations or read-while-erase operations.
FIGS. 2 and 3 depict conventional memory devices 30 and 50 that can perform read-while-write operations or read-while-erase operations. In order to do so, each of the conventional memory devices 30 and 50 is broken into banks. For example, FIG. 2 depicts the conventional memory device 30, which has n banks 31. Each bank 31-i includes an array 32-i of conventional storage cells (not explicitly shown). The conventional memory 30 includes an x decoder 34-i, and a column decoder 36-i for each bank 31. Common sense circuitry is, however, used. Consequently, the circuitry used for reading and verifying the data is shared between all of the banks 31. Thus, the modify sense amplifier block 38, sense amplifier read block 40, high voltage switches 42, data multiplexer 44, and programming logic 46 are used for all arrays 31-3 through 31-n. The modify sense amplifier block 38 is connected to the write bit line 47, while the sense amplifier read block 40 is coupled to the read bit line 48. Programming logic 46 controls the high voltage switches 42.
Although the conventional memory device 30 functions, one of ordinary skill in the art will readily recognize that there are issues with such an architecture. In particular, offsets in the sense circuitry 38 and 40 reduce the margin allowed for reading current from a particular cell in the array 32-i, as well as a reference current, are reduced. Thus, it may be more difficult to accurately determine the data stored in a cell. The coupling of the modify sense amplifier block 38 to the write bit line 47 and the sense amplifier read block 40 to the read bit line 48 may introduce coupling between the signal being output using the read bit line 47 and the data in arrays 32-i below the read bit line 47.
FIG. 3 depicts the conventional memory device 50, which has m banks 60-1 through 60-m. Each bank 60-i includes an array 62-i of conventional storage cells (not explicitly shown). The conventional memory 60 includes an x decoder 64-i, and a column decoder 66-i for each bank 60-i. In addition, the sensing circuitry is local to each bank 60-i. Thus, the sense amplifier block 68-i, high voltage switches 70-i, data multiplexer 72-i, and programming logic 74-i are used for each array 60-1 through 60-m. Each bank 60-i thus includes reading and verifying circuitry for each bank 60-i. 
Use of the conventional memory device 50 avoids some of the issues of the conventional memory device 30. All sensing and addressing circuitry is local to each bank 60-i. Consequently, the offsets and coupling described above are avoided. However, the area occupied by the conventional memory 60 has increased significantly, which is undesirable. In addition, because the area consumed by the sensing circuitry 68-1 through 68-m, 70-1 through 70-m, 72-1 through 72-m, and 74-1 through 74-m, routing of sensing signals is made significantly more difficult.
Accordingly, what is needed is a mechanism for more efficiently performing read-while-write and read-while-erase operations while allowing the memory to consume less area. The present invention addresses such a need.